Journal of South China University of Technology (Natural Science Edition) ›› 2017, Vol. 45 ›› Issue (3): 42-47.doi: 10.3969/j.issn.1000-565X.2017.03.006

• Electronics, Communication & Automation Technology • Previous Articles     Next Articles

Design of a Low-Power Consumption D Flip - Flop on the Basis of a-IGZO TFTs

YAO Ruo-he LIN Shao-long   

  1. School of Electronic and Information Engineering,South China University of Technology,Guangzhou 510640,Guangdong,China
  • Received:2016-05-29 Revised:2016-10-25 Online:2017-03-25 Published:2017-02-02
  • Contact: 姚若河( 1961-) ，男，教授，博士生导师，主要从事集成电路系统设计、半导体物理及器件研究． E-mail:phryao@scut.edu.cn
  • About author:姚若河( 1961-) ，男，教授，博士生导师，主要从事集成电路系统设计、半导体物理及器件研究．
  • Supported by:
    Supported by the National Natural Science Foundation of China( 61274085) and the Science and Technology Research Projects of Guangdong Province( 2015B090909001)

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Abstract:

Proposed in this paper is a low-power consumption D flip-flop circuit with asynchronous reset on the basis of Pseudo-CMOS logic gates,which consists of n-type a-IGZO TFTs ( Thin Film Transistors) ,replaces the diodeload in Pseudo-CMOS topology with dynamic load,and decreases the static power consumption by reducing the conduction probability of the circuit.The output stage of the circuit is a latch,and the effect of dynamic loadcaused output swing decrement on the delay is reduced through a feedback path.The proposed D flip-flop is then applied to the design of a ring shift register.The results show that the trigger circuit can reduce the static power consumption in NOR gate logic circuit effectively.

Key words: thin film transistor, D flip-flop, dynamic load, shift register

CLC Number: