Journal of South China University of Technology (Natural Science Edition) ›› 2013, Vol. 41 ›› Issue (5): 34-42.doi: 10.3969/j.issn.1000-565X.2013.05.006

• Electronics, Communication & Automation Technology • Previous Articles     Next Articles

Boolean Matching of Wide Functions and Its Application to Resynthesis of FPGA

Zhang Feng1 Wang Zuo-jian2 Wu Yang2 Yu Fang1 Liu Zhong-li1   

  1. 1.Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China;2.Uptops Design Technologies,Inc.,Beijing 100029,China
  • Received:2012-08-22 Revised:2013-01-21 Online:2013-05-25 Published:2013-04-01
  • Contact: 张峰(1987-) ，男，博士生，主要从事FPGA EDA 工具的设计与研究． E-mail:zhangfeng08@yeah.net
  • About author:张峰(1987-) ，男，博士生，主要从事FPGA EDA 工具的设计与研究．

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Abstract:

The configurable logic block ( CLB) of the existing commercial FPGAs ( Field Programmable GateArrays) comprises not only lookup table ( LUT) but also many assistant logic resources that cannot be fully utilizedby the conventional LUT-based mapping algorithms.In order to solve this problem,a Boolean matching method forpost-mapping resynthesis is proposed based on the Shannon expansion and the DSD ( Disjoint Support Decomposition)algorithm.This method helps to implement the Boolean matching of wide functions of mapped LUTs and reimplementthe wide functions with target FPGA CLB,so as to make full use of all logic resources in CLB and reducethe number of LUTs.From the mapped results generated by state-of-the-art FPGA mapper ABC,it is foundthat the proposed method reduces the number of LUTs respectively by 7.9% for 4-LUT networks and by 7.8% for6-LUT networks while preserving the logic depth.

Key words: electronic design automation, field programmable gate array, Boolean matching, wide function, resyn-thesis, configurable logic block, lookup table

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