Journal of South China University of Technology(Natural Science Edition) ›› 2012, Vol. 40 ›› Issue (6): 16-21.

• Electronics, Communication & Automation Technology • Previous Articles     Next Articles

Implementation of Placement and Routing Improvement for Island-Style FPGA Chips

Li Ming  Li Yan  Chen Liang  Yu Fang  Liu Zhong-li   

  1. Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China
  • Received:2011-12-26 Revised:2012-03-28 Online:2012-06-25 Published:2012-05-03
  • Contact: 李明(1985-) ,男,博士生,主要从事FPGA EDA 工具的布局布线及GUI 实现研究. E-mail:mzliming@126.com
  • About author:李明(1985-) ,男,博士生,主要从事FPGA EDA 工具的布局布线及GUI 实现研究.
  • Supported by:

    “核高基”国家科技重大专项( Y1GZ212002)

Abstract:

In order to overcome the loose coupling between FPGA ( Field Programmable Gate Array) placement and routing,an improved placement and routing tool named IVPR is exploited. In IVPR,the directions of logic block pins are considered during the placement to perform a more precise delay forecast,and the possible directions of logic block pins during the routing are predicted to choose an appropriate delay. Thus,the combination between the placement and the routing becomes more effective. Moreover,for the high fanout in the netlist,the net terminal alignment is employed during the placement and the longline-priority strategy is adopted during the routing. Tested results on an island-style FPGA chip VS1000 show that,as compared with the typical placement and routing tool VPR,IVPR reduces the circuit delay by 16.4% and increases the routing resource utilization by 1.9%.

Key words: field programmable gate array, placement, routing, delay forecast, net terminal alignment

CLC Number: