Abstract: Abstract: In some of the process of dealing with high performance chip physical design, there may encounter the problem caused by crossbar structure. These paths generated by crossbar cause logic cluster together and always lead to congestion or badly timing. These features of crossbar structure make it difficult for P&R tools (ICC, ICC2, Encounter, innovus, etc.) to obtain a satisfied result. This is especially serious in advanced node design with tension routing resource. In this paper, we propose a new structural placement method to solve the problem caused by the crossbar. In the previous structural placement studies, the focus is often on the timing optimization of the data path, and does not involve the requirement of inserting a large number of buffers. The proposed new structural placement method, can successfully solve the routing congestion and the induced timing problem through inserting the buffer tree by fully considering the characteristics of the crossbar. After using the proposed structural placement, the crossbar module TNS (total negative slack) was decreased from -29 ns to -1.7 ns, the WNS (worst negative slack) was increased from -53 ps to -38 ps, the total DRC errors number was decreased from 7094 to 352 and the total net length of crossbar was decreased from 772076 mm to 442066 mm. And considerable improvement was also achieved to other modules of the design.

Key words: chip layout, crossbar structure, structure placement, physical design