Abstract:

In order to speed up the startup of phase-locked loop（PLL）,an initialization circuit is proposed,which stops working after the startup has been finished and consumes little power.Then,a phase-frequency detctor（PFD） with saturated output is proposed to extend the working range of PFD.Moreover,a logic circuit is applied to directly control a standard counter and to simplify the pulse-swallow frequency divider into a single loop,thus saving a counter without increasing the power consumption.Finally,the standard CMOS logic process of 0. 18 μm 1.8 V 1P6M N trap is applied to the design with a layout area of 0. 08mm². Simulated results show that the application of both the initial circuit and the PFD with saturated output results in a decrease of locking time by 19% , and that, at a frequency of 266 MHz, the relative peak-peak jitter of the output signal is less than 2.5% and the total power consumption of the PLL is about 17 mW.

Key words: charge pump, phase-locked loop, initialization, saturated output, fast locking, power consumption