Abstract:

In order to meet the requirements of miniaturization,low power consumption,low cost and high precision of the embedded integrated navigation system based on the digital signal processor（DSP）,single field programmable gate array（FPGA） chip was used to control each logic module,expand the multi-channel universal asynchronous receiver transmitter（UART） and design double first-in-first-out（FIFO） memories for the data buffering of UART.In addition,for the purpose of reducing the additional CPU overhead for transmission, a Ping-Pong Buffer storage was designed in the random access memory （RAM） of DSP, and the enhanced direct memory access （EDMA） provided by TMS320C6713 was used to transmit data between the FIFO of UART in FPGA and the Ping-Pong Buffer storage. Test results indicate that the proposed scheme makes the multi-channel UART steadily operate at 460. 8 kb/s with the control of EDMA when CPU executes navigation algorithms at the same time. Thus, a high-speed communication chain between DPS and peripheral equipment is successfully implemented and CPU can be devoted further to navigation algorithms.

Key words: global positioning system, inertial navigation system, digital signal processor, field programmable gate array, serial communication, enhanced direct memory access