Abstract: A large quantity of matrix multiplier calculations must be executed in the iterative calculation of the inverter harmonic elimination PWM model．In order to fasten the calculation speed a matrix multiplier which is based on2-D square systolic array architecture is introduced in this paper in light of the parallel algorithm of matrix computation．The implementation of this matrix multiplier used by FPGA is analyzed and a comparison is made in terms of the computation speed and occupied hardware resources between the single processing element matrix multiplier and the2-D square systolic array architecture matrix multiplier．The research results show that the matrix multiplier based on2-D square systolic array architecture possesses advantages of parallel processing and flow computation．It can unify the load shorten the delay and increase the level of integration．It has proved to be a good algorithm of matrix multiplier computation with regard to the inverter harmonic elimination model calculation．

Key words: harmonic elimination model, matrix multiplier, systolic array