关键词: 电子设计自动化, 现场可编程门阵列, 布尔匹配, 宽函数, 重综合, 可配置逻辑块, 查找表

Abstract:

The configurable logic block ( CLB) of the existing commercial FPGAs ( Field Programmable GateArrays) comprises not only lookup table ( LUT) but also many assistant logic resources that cannot be fully utilizedby the conventional LUT-based mapping algorithms.In order to solve this problem,a Boolean matching method forpost-mapping resynthesis is proposed based on the Shannon expansion and the DSD ( Disjoint Support Decomposition)algorithm.This method helps to implement the Boolean matching of wide functions of mapped LUTs and reimplementthe wide functions with target FPGA CLB,so as to make full use of all logic resources in CLB and reducethe number of LUTs.From the mapped results generated by state-of-the-art FPGA mapper ABC,it is foundthat the proposed method reduces the number of LUTs respectively by 7.9% for 4-LUT networks and by 7.8% for6-LUT networks while preserving the logic depth.

Key words: electronic design automation, field programmable gate array, Boolean matching, wide function, resyn-thesis, configurable logic block, lookup table