Proposed in this paper is a low-power consumption D flip-flop circuit with asynchronous reset on the basis of Pseudo-CMOS logic gates,which consists of n-type a-IGZO TFTs ( Thin Film Transistors) ,replaces the diodeload in Pseudo-CMOS topology with dynamic load,and decreases the static power consumption by reducing the conduction probability of the circuit.The output stage of the circuit is a latch,and the effect of dynamic loadcaused output swing decrement on the delay is reduced through a feedback path.The proposed D flip-flop is then applied to the design of a ring shift register.The results show that the trigger circuit can reduce the static power consumption in NOR gate logic circuit effectively.