Abstract:

In the field programmable gate array (FPGA),the quantity of arithmetic resources which need more area than normal logic resources is limited,and most of the RTL (Register Transfer Level) synthesis algorithms only focus on normal logic resources.In order to solve these problems,a method of priority resource sharing is pro-posed.This method improves normal resource sharing methods and makes two or more arithmetic logic units (ALUs) operating at different time to share the resources in a priority order of ALUs having the same output,ALUs having the same input and ALUs having different ports.Experimental results show that the proposed method reduces the number of ALUs and implements the area optimization in FPGA; and that,as compared with normal resource sharing methods,it costs less multiplexers,achieves better timing results and avoids data flow conflicts.

Key words: resource sharing, field programmable gate array, register transfer level, synthesis, arithmetic logic unit, area optimization