Abstract:

Based on Daemen’s AES fast algorithm,two schemes of implementing the instruction set extension on configurable processor NiosII are proposed to achieve hardware acceleration. These two schemes,one of which stores lookup table in on-chip memory and the other uses a logic circuit to realize the S-box and calculates the corresponding elements of the lookup table,employ a forward lookup table to replace the intensive round transformation
operation. Specifically,the forward lookup table of the fast algorithm is placed in on-chip memory,12 new extended instructions are created to achieve the key expansion,the round transformation and the last round transformation,and the S-box used in the last round is obtained by masking the forward look-up table. In order to eliminate the on-chip memory usage,the schemes are then optimized by deriving the logical relationship between the S-box and the forward lookup table and by employing a logic circuit to realize the S-box via the inverse finite element method. Thus,the system security is enhanced and the power consumption is reduced. Finally,the performances of the extended instruction sets,the coprocessor and some other schemes are tested and compared. The results show that,as compared with the pure software solution of AES fast algorithm with optimized structure,the proposed schemes increase the speedup by 247% only with 223 additional LEs.

Key words: AES fast algorithm, extended instruction set, S-box, finite field, NiosII processor, speedup