Journal of South China University of Technology (Natural Science Edition) ›› 2009, Vol. 37 ›› Issue (9): 67-70,81.

• Electronics, Communication & Automation Technology • Previous Articles     Next Articles

Design of Low-Clock Jitter VCO with Strong Ability of Rejecting Power Supply Noise

Cai Min  Wang Dong-chun   

  1. School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510640, Guangdong, China
  • Received:2008-07-25 Revised:2009-03-05 Online:2009-09-25 Published:2009-09-25
  • Contact: 蔡敏(1955-),男,教授,博士生导师,主要从事集成电路设计与系统集成研究. E-mail:admincai@seut.edu.cn
  • About author:蔡敏(1955-),男,教授,博士生导师,主要从事集成电路设计与系统集成研究.

Abstract:

A kind of ring voltage-controlled oscillator(VCO) based on the current steering logic is designed,and the conventional cascode bias circuit is improved by introducing a amplifier with large voltage gain to constitute a new active negative feedback structure with strong ability of rejecting power supply noise.Then,a contrast simulation of the conventional VCO and the improved one is conducted with HEJIAN 0.18μm twin-well CMOS technology.The results indicate that the peak-peak jitter and the RMS(Root Mean Square) jitter of the conventional VCO are respectively 54. 135 ps and 19. 454 ps under the high-frequency power supply noise with a frequency of 20 MHz and a peak-peak amplitude of 0. 2 V, while the corresponding values of the improved VCO are respectively 27. 442 ps and 9. 196 ps, which reveals better jitter performance of the improved VCO. Moreover, the improved VCO is of an output frequency of650MHz, a duty cycle of about 52%, a voltage gain of 962. 16 MHz/V for a central control voltage of 0. 9 V with good linearity, and a low power dissipation of only about 0. 7 mW in 1.8 V DC power supply.

Key words: current steering logic, voltage-controlled oscillator, negative feedback, jitter