Journal of South China University of Technology (Natural Science Edition) ›› 2008, Vol. 36 ›› Issue (9): 128-131.

• Electronics, Communication & Automation Technology • Previous Articles     Next Articles

Design of CMOS Voltage Reference for Low Voltage and Low Power Consumption

Cai Min  Shu Jun   

  1. School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510640, Guangdong, China
  • Received:2007-09-19 Revised:2008-01-07 Online:2008-09-25 Published:2008-09-25
  • Contact: 蔡敏（1955-），男，教授，博士生导师，主要从事集成电路设计与系统集成研究． E-mail:admincai@scut．edu．cn.
  • About author:蔡敏（1955-），男，教授，博士生导师，主要从事集成电路设计与系统集成研究．

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Abstract:

In order to effectively decrease the power consumption of analog integrated circuits and improve the technology compatibility, a design method of low-voltage low-power consumption voltage reference with fully CMOS configuration is presented based on the MOS transistors in sub-threshold region. In this method, the negative feedback system constructed by the PTAT current source and the micropower operation amplifier is employed to improve the power-supply rejection ratio （PSRR）. Simulated results demonstrate that, with a power supply voltage of 1.0 V, the circuit exhibits an output voltage of 609mV, a temperature coefficient of 46 × 10^-6/K and a total power supply current of 1.23 μA, that when the supply voltage ranges from 1.0~ to 5.0V, the power supply is of a voltage sensitivity of 130 μV/V and a low-frequency PSRR of 74. 0 dB, and that the proposed circuit has good compatibility for CMOS technology due to the adopted full CMOS construction without parasitic bipolar junction transistors.

Key words: voltage reference, power consumption, power-supply rejection ratio, sub-threshold