Journal of South China University of Technology (Natural Science Edition) ›› 2007, Vol. 35 ›› Issue (6): 50-53,75.

• Physics • Previous Articles     Next Articles

Design and Implementation of Fractiona-lN PLL Based on MASH 2-1 Architecture

Deng Wan-ling  Zheng Xue-ren  Liu Wei-jian   

  1. Microe lectron ics Institute, South Ch ina Un iv. o f Tech. , Guang zhou 510640, Guangdong, Ch ina
  • Received:2006-04-04 Online:2007-06-25 Published:2007-06-25
  • Contact: 邓婉玲(1980-), 女, 博士生, 主要从事集成电路设计与验证研究. E-mail:dwanl@126. com
  • About author:邓婉玲(1980-), 女, 博士生, 主要从事集成电路设计与验证研究.

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Abstract:

A digital ΔΣ modu latorw ith a three-order MASH (Mu lt-i Stage no ise SH aping) 2-1 arch itecture is designedand imp lemented, whose advantages in noise shap ing is then verif ied by the resu lts ofMa tlab simu lation.Then, a type-Ⅱfour-order phase-locked loop ( PLL) emp loy ing the ΔΣ modu lator based on MASH 2-1 is presented.According to the resu lts of the correspond ingM atlab simulation and the frequency spectrum measurement ,it is found that the stable output frequency of PLL meets the design requirement

Key words: Mult-i Stage noise SHaping, Δ&Sigma, modulator, fractiona-lN, phase-locked loop