Journal of South China University of Technology (Natural Science Edition) ›› 2005, Vol. 33 ›› Issue (6): 5-8.

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Clock Tree Analysis in Design of Synchronous Digital Integrated Circuit

Yin Rui-xiang  Guo Rong  Chen Min   

  1. College of Electronic and Information Engineering,South China Univ.of Tech.,Guangzhou 510640,Guangdong,China
  • Received:2004-09-27 Online:2005-06-25 Published:2005-06-25
  • Contact: 殷瑞祥(1960-),男,博士,教授,主要从事信号与信息处理、大规模集成电路设计方面的研究 E-mail:etrxyin@ scut.edu.cn
  • About author:殷瑞祥(1960-),男,博士,教授,主要从事信号与信息处理、大规模集成电路设计方面的研究

Abstract:

In designing synchronous digital integrated circuits,the design of clock tree is an important component,which may greatly affect the performance and reliability of the system. In this paper. the constitution of the syn.chronous digital system and the definition of clock skew are introduced,and a designing method for clock tree is presented.Based on the proposed method,the automatic clock tree synthesis and the structure-specified clock tree
synthesis of 8051 chip are then perform ed using Astro.The results indicate that,compared with the results obtained by the automatic clock tree synthesis,better results can be obtained by the proposed method. Moreover,the solu-tion to the gate clock is presented.

Key words: synchronous digital system , integrated circuit design, clock tree, clock skew