Abstract: In the solution of the harmonic elimination PWM model for inverted power supply‚the inverse calculation of Jacobi matrix is the main factor affecting the solving speed．In this paper‚to accelerate the solving speed of Jacobi matrix‚the Gausssian elimination was briefly analyzed‚on the basis of which a circuit structure of LU decomposition realized by a two-dimension systolic array was constructed．The structure was then modeled and simulated by VHDL language and its validity was verified by FPGA experiments．The results show that the proposed structure can be used to realize the rapid LU decomposition of the matrix‚thus effectively improving the rea-l time property of the solution of the harmonic elimination model． 

Key words: systolic array, LU decomposition, harmonic elimination PWM, FPGA