Abstract: To reduce the FPGA resources that RS decoder occupies‚the algorithm of RS decoding was studied．An approach to implement RS decoding in IP block error correction system on Actel ProASIC PLUS chip was also presented． In this approach‚RS（100‚81） was adopted for error correction．Based on the complicated operation‚the solution to the decoder‚that is‚the modified BM algorithm‚was then described‚which can save more resources than the traditional one．Experimental results indicate that the decoder can accomplish the task of IP block error correction and can accept an input data rate up to30Mbit／s．The primary architecture of ProASIC PLUS chip and the key technology of its implementation on FPGA were finally presented．

Key words:  IP block, RS code, decoder, modified BM algorithm, field programmable gate array