Abstract: The application of failure restraint (FR) technology in synchronous digital hierarchy (SDH) , the design theory and realization process of FR system are discussed in this paper. One method to implement FR system by using a DSP series port DMA is presented and the key technology of the whole scheme is analyzed in detail. The experimental results prove the validity of this method and some methods to further improve the FR system are put forward.

Key words: digital signal processor, synchronous digital hierarchy, failure restraint, network management tech-nology