Abstract:

In order to improve the speed and reduce the area of fixed- point multipliers,odd multiple of partialproducts is represented with the redundant differential based on the Radix- 16 redundant parallel multiplier.Then,the correction words of partial products and the partial products are compressed to reduce the number of partialproducts.Through optimizing the structures of the control signal generator,the Booth decoder and the binary con-verter,the time delay and the area of the multiplier are further reduced.Finally,the modified multiplier is synthe-sized by Design Complier with the TSMC 180nm library,with an area decrement of 8% and a delay reduction of11% being obtained.

Key words: multiplier, redundancy, logic design, encoding, computational method