Two-point modulation phaselocked loop ( PLL) for Bluetooth polar transmitter was studied and designed by using 0. 11μm 1P6M CMOS process． In order to correct the loop gain of two phase modulation paths in the PLL and reduce the frequency shift keying error of using the phaselocked loop，a new gain correction method was proposed． And a new phaselocked loop circuit of two-point modulation based on gain calibration was proposed to reduce phase noise of PLL and accelerate the locking time of phaselocked loop． Chip measured results show that when voltage controlled oscillator oscillates at 4. 8 GHz，the phase noises at 10 kHz，1 MHz，3 MHz offsets are －83dBc/Hz， －108dBc/Hz and －114dBc/Hz，respectively． When using the polar transmitter of phaselocked loop to transmit the 0dBm signal，the FSK error is 2. 97%，and the phaselocked loop occupies 0. 32 mm2． The overall performance meets the requirements of Bluetooth ＲF chip test specification．