Electronics, Communication & Automation Technology

Defect Localization Method of 3D Stacked-Die Packaged Integrated Circuits

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  • 1.Science and Technology on Reliability Physics and Application of Electronic Component Laboratory,The Fifth Electronics Research Institute of the Ministry of Industry and Information Technology,Guangzhou 510610,Guangdong,China; 2.School of Electronic and Information Engineering,South China University of Technology,Guangzhou 510640,Guangdong,China
林晓玲(1978-),女,博士,高级工程师,主要从事微电子可靠性物理、IC 失效分析技术研究. E-mail:lin_x_l@ 163. com

Received date: 2015-07-22

  Revised date: 2015-10-20

  Online published: 2016-04-12

Supported by

Supported by the Natural Science Foundation of Guangdong Province(2014A030313656)

Abstract

Three-dimension (3D) stacked-die package is one of the important package types of high-performance devices.Its unique packaging brings new challenges to defect localization.In this paper,a localization method of defects inside 3D stacked-die packaged integrated circuits,which integrates both lock-in thermography imaging and X-ray detection technology,is proposed.Firstly,X-ray detection technology is used to obtain internal structure of the device horizontally and vertically,and thus the chip location and size,the stack layers and the wire bonding mode inside the package can be determined.Secondly,the propagation delay information of defects inside package and the defect location on xy plane are obtained via lock-in thermography imaging.Then,more exact location in- formation of the defect in z direction is obtained by calculating the phase shift at different frequencies.Finally,some experiments are carried out to discover the localization of defects inside a plastic packaging SDRAM,and the corresponding physical analysis is made.The results show that the integration of lock-in thermography imaging with X-ray detection technology helps localize defects of 3D stacked-die packaged devices without decapping the device.

Cite this article

LIN Xiao-ling EN Yun-fei YAO Ruo-he . Defect Localization Method of 3D Stacked-Die Packaged Integrated Circuits[J]. Journal of South China University of Technology(Natural Science), 2016 , 44(5) : 36 -41,47 . DOI: 10.3969/j.issn.1000-565X.2016.05.006

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