Abstract:

In order to avoid the failure lock and harmonic lock in conventional delay-locked loop（DLL） during wide-range operation,a start control circuit is added in the conventional DLL structure to charge the power supply by the loop filter capacitor in the power-on stage.So,the intitial delay of voltage-controlled delay line（VCDL） is minimized after the power-on and is controlled to be less than one period of the input reference clock.Then,a novel phase detector with switches is designed,which divides the locking process of DLL into a coarse tuning stage and a fine one.In the coarse tuing stage,the delay of VCDL monotonically increases,while in the fine stage,it is fine tuned till to one period of the input reference clock.Thus,the failure lock and harmonic lock during wide-range operation are successfully avoided and the the locking time of DLL is reduced.Finally,a DLL is designed and simulated under the power supply of 1.2V with GSMC 0.13μm 1P7M CMOS technology,with an operation frequency of 300～500MHz and a power consumption of less than 3mW being achieved.

Key words: phase-locked loop, start control circuit, phase detector, harmonic lock