Abstract:

In order to improve the performance of integer discrete wavelet transform （DWT） and the compression quality of images, a DWT architecture with high performance and low memory is proposed for JPEG2000. This architecture extends the precision of raw image data and effectively preserves the fractional bits of transformed coeffi- cients in lifting steps. It adopts a memory scheme of wavelet coefficients based on code block strips to reuse and schedule the memories with code block strips in sub-bands, thus reducing the hardware resources in terms of sto- rage and power consumption. Experimental results show that the proposed scheme effectively improves the compres- sion quality of images, and that, by decomposing a 512 × 512 image using a code block in the size of 32 × 32, the memory of the proposed architecture is only 20% that of the scheme directly buffering all the coefficients in the transformed image. The proposed architecture has passed the FPGA verification and the synthesized clock frequency of it is up to 150 MHz

Key words: JPEG2000, discrete wavelet transform, lifting scheme, code block, VLSI circuits