Abstract: Existing works based on Tiny-yolo often need large-scale network model，occupy more memories，rely on massive calculation and are not easy to deploy on embedded devices． To solve these problems，an efficient optimi- zation method on network compression and hardware acceleration was proposed． Firstly，connections which have less contribution to the network was pruned after analyzing the network connection relationship and sparse storage was adopted for the clipped weight matrix to reduce the memory consumption． Secondly，memory footprint and com- putational complexity within the guaranteed accuracy error was further reduced through quantifying the weight data and changing the number of digits． Finally，according to the characteristics of the Tiny-yolo network structure，a deep parallel-stream FPGA acceleration optimization scheme was proposed and the hardware acceleration of the Ti- ny-yolo network computation was achieved． Experiments demonstrate that the purposed method based on network pruning and quantization can achieve about 36X compression for network model and approximately 7X speedup compared with CPU by hardware acceleration．

Key words: neural network, Tiny-yolo, compression, hardware acceleration, FPGA