为提高定点乘法器速度，减少乘法器面积，基于 Radix- 16 冗余并行乘法器，将奇数倍部分积用冗余差分形式表示;将部分积的修正位与部分积进行压缩，减少了部分积数量;通过优化控制信号产生电路、Booth 解码电路和二进制转换电路的结构，进一步减少了乘法器延时和面积．TSMC 180nm 工艺下的 Design Complier 综合结果表明，改进后冗余乘法器的面积相对减少 8%，延时相对减少 11%．

In order to improve the speed and reduce the area of fixed- point multipliers,odd multiple of partialproducts is represented with the redundant differential based on the Radix- 16 redundant parallel multiplier.Then,the correction words of partial products and the partial products are compressed to reduce the number of partialproducts.Through optimizing the structures of the control signal generator,the Booth decoder and the binary con-verter,the time delay and the area of the multiplier are further reduced.Finally,the modified multiplier is synthe-sized by Design Complier with the TSMC 180nm library,with an area decrement of 8% and a delay reduction of11% being obtained.