华南理工大学学报(自然科学版) ›› 2015, Vol. 43 ›› Issue (9): 47-53,66.doi: 10.3969/j.issn.1000-565X.2015.09.008

• 电子、通信与自动控制 • 上一篇    下一篇

应用于 SAR ADC 的高能效电容阵列 DAC

胡云峰1,2 ,李斌1†,吴朝晖1   

  1. 1. 华南理工大学 电子与信息学院,广东 广州 510640; 2. 电子科技大学中山学院,广东 中山 528402
  • 收稿日期:2015-03-17 修回日期:2015-04-22 出版日期:2015-09-25 发布日期:2015-09-07
  • 通信作者: 李斌(1967-),女,教授,博士生导师,主要从事半导体器件与模拟集成电路研究. E-mail:phlibin@scut.edu.cn
  • 作者简介:胡云峰(1982-),男,在职博士生,电子科技大学中山学院讲师,主要从事逐次逼近型模数转换器研究. E-mail: shanhuyf@163.com
  • 基金资助:
    国家自然科学基金资助项目(60976026);国家自然科学基金面上项目(61571196)

High Energy-Efficient Capacitor Array DAC for SAR ADC

Hu Yun-feng1,2  Li Bin1  Wu Zhao-hui1   

  1. 1. School of Electronic and Information Engineering,South China University of Technology,Guangzhou 510640,Guangdong,China; 2. Zhongshan Institute,University of Electronic Science and Technology of China,Zhongshan528402,Guangdong,China
  • Received:2015-03-17 Revised:2015-04-22 Online:2015-09-25 Published:2015-09-07
  • Contact: 李斌(1967-),女,教授,博士生导师,主要从事半导体器件与模拟集成电路研究. E-mail:phlibin@scut.edu.cn
  • About author:胡云峰(1982-),男,在职博士生,电子科技大学中山学院讲师,主要从事逐次逼近型模数转换器研究. E-mail: shanhuyf@163.com
  • Supported by:
    Supported by the National Natural Science Foundation of China(60976026) and the General Program of the
    National Natural Science Foundation of China(61571196)

摘要: 电容阵列数模转换器( DAC) 是逐次逼近型模数转换器( SAR ADC) 的主要能耗来源之一. 为降低电容阵列 DAC 的能耗,提出了一种高能效电容阵列 DAC 结构,该结构电容阵列中各电容单元通过开关依次连接. 在前两次比较周期中,由于采用了顶板采样和电压移位技术,电容阵列 DAC 没有产生能耗; 在之后的比较周期中,由于采用电荷共享和电压单调降低技术,电容阵列 DAC 产生了很少的能耗. 仿真结果表明,相比于传统的电容阵列 DAC
结构,文中提出的高能效电容阵列 DAC 结构可降低99. 22%的能耗,节省75%的面积.

关键词: 逐次逼近寄存器, 模数转换, 电容阵列 DAC, 高能效

Abstract: Capacitor array digital-to-analogue converter (DAC) is one of the main energy consumption sources of
successive approximation register analogue-to-digital converter (SAR ADC). In order to reduce the energy consumption of capacitor array DAC,this paper proposes a high energy-efficient capacitor array DAC structure. In the structure,each capacitor part is connected in turn through a switch. In the first two comparison cycles,owing to the top-plate sampling technique and the level shift technique,there is no switching energy consumption in the capacitor array DAC; in the rest of comparison cycles from the third to the nth,owing to the charge sharing technique and the voltage monotonic down technique,there exists a low switching energy consumption in the capacitor array DAC.
Simulation results show that,in comparison with the traditional capacitor array DAC structure,the proposed struc-
ture can decrease the energy consumption by 99. 22% and reduce the number of capacitors by 75%.

Key words: successive approximation register, analog to digital conversion, capacitor array DAC, high energy-efficiency

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