华南理工大学学报(自然科学版) ›› 2015, Vol. 43 ›› Issue (1): 15-20.doi: 10.3969/j.issn.1000-565X.2015.01.003

• 电子、通信与自动控制 • 上一篇    下一篇

用于生物医学信号采集的高PSRR及CMRR的植入式模拟前端

吴朝晖 谢宇智 赵明剑 李斌   

  1. 华南理工大学 电子与信息学院, 广东 广州 510640
  • 收稿日期:2014-03-19 修回日期:2014-10-16 出版日期:2015-01-25 发布日期:2014-12-01
  • 通信作者: 吴朝晖(1971-),男,博士,副教授,主要从事模数混合及模拟芯片设计研究 . E-mail:phzhwu@scut.edu.cn
  • 作者简介:吴朝晖(1971-),男,博士,副教授,主要从事模数混合及模拟芯片设计研究 .
  • 基金资助:

    广东省自然科学基金博士科研启动项目( 2014A030310372 )

Implantable Analog Front-End with High PSRR and CMRR for Neural Signal Acquisition

Wu Zhao-hui Xie Yu-zhi Zhao Ming-jian Li Bin   

  1. School of Electronic and Information Engineering , South China University of Technology , Guangzhou 510640 ,Guangdong , China
  • Received:2014-03-19 Revised:2014-10-16 Online:2015-01-25 Published:2014-12-01
  • Contact: 吴朝晖(1971-),男,博士,副教授,主要从事模数混合及模拟芯片设计研究 . E-mail:phzhwu@scut.edu.cn
  • About author:吴朝晖(1971-),男,博士,副教授,主要从事模数混合及模拟芯片设计研究 .
  • Supported by:
    Supported by the PhD Start-up Fund of Natural Science Foundation of Guangdong Province ( 2014A030310372 )

摘要: 针对人体内神经电信号非常微弱、噪声大、环境干扰大等特点,研究与设计了一款应用于神经信号采集的高电源抑制比( PSRR )和共模抑制比( CMRR )的低噪声植入式模拟前端 . 该模拟前端采用全差分结构来实现模拟前端中的前置放大器、开关电容滤波器及可变增益放大器,使得电路具有较好的电源抑制比和共模抑制比;采用斩波调制技术来抑制电路的低频噪声,并通过带电流数模转换器( DAC )的纹波抑制环路来抑制前置放大器的输出纹波,从而使该模拟前端在具有高 PSRR 和 CMRR 的同时能保持低噪声性能 . 文中采用 0.18μm CMOS 工艺设计该模拟前端芯片,版图后仿真结果表明,该模拟前端在
0.1Hz~10kHz 内的等效输入噪声为 2.59μV , 实现了 46.35 、 52.18 、 60.02 、 65.95dB 可调增益, CMRR 和 PSRR 分别可达146 及 108dB ,很好地满足了植入式神经信号采集的要求

关键词: 神经信号, 模拟电路, 模拟前端, 植入式器件, 高电源抑制比, 高共模抑制比

Abstract: As the in vivo electroneurographic signals are weak with high noise and strong environment interference , an implantable low-noise analog front-end with high power supply rejection ratio ( PSRR ) and com-mon mode rejection ratio ( CMRR ) for neural signal acquisition is proposed. Fully differential structure is used to design the preamplifier , switch capacitor filter and variable gain amplifier of the analog front-end. Chopper stabilization technology is used to reduce the low-frequency noise and a ripple reduction loop with current DAC is used to reduce the output ripple. In this way , the proposed analog front-end can achieve high PSRR and CMRR without increasing the original low noise. Moreover , a front-end chip is designed via 0.18μm CMOS technology and is used for simulation. The results of layout show that ( 1 ) input-referred noise of the analog front-end is 2.6μV at the interval of 0.1Hz~10kHz ;( 2 ) the gain of the analog front-end can switch among 46.35 , 52.18 , 60.02 and 66.95dB ; and ( 3 ) the CMRR and PSRR of the analog front-end are respectively 146 and 108 dB. Thus , it draws the conclusion that the proposed analog front-end is suitable for neural signal acquisition.

Key words: neural signal, analog circuit, analog front-end, implantable devices, high PSRR, high CMRR

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