收稿日期: 2010-05-05
修回日期: 2010-06-27
网络出版日期: 2011-02-01
基金资助
电子元器件可靠性物理及其应用技术国家重点实验室基金资助项目(9140C0301040801)
Effect of Via Microstructure on Cu/low-k Stress-Induced Voiding
Received date: 2010-05-05
Revised date: 2010-06-27
Online published: 2011-02-01
Supported by
电子元器件可靠性物理及其应用技术国家重点实验室基金资助项目(9140C0301040801)
林晓玲 侯通贤 章晓文 姚若河 . 通孔微结构对Cu/低-k应力诱生空洞的影响[J]. 华南理工大学学报(自然科学版), 2011 , 39(3) : 135 -139 . DOI: 10.3969/j.issn.1000-565X.2011.03.026
Based on the kinematic hardening model of copper,the Cu stress in different Cu/low-k via microstructures are modeled and analyzed via the finite element method to explore the changes of via height,via gouging depth and barrier layer thickness at the via bottom due to the process variation of interconnected via and via barrier layer.Then,the corresponding interconnected via and bottom interconnection stress-induced voiding(SIV) varying with the changes are analyzed.The results indicate that the via microstructure effect of Cu/low-k interconnection is a dominated factor affecting the interconnection stress and the SIV,that the via with high aspect ratio is more susceptible to SIV due to height variation,that the via gouging with suitable depth effectively improves the reliability of stress migration,and that the interconnection SIV performance and the thickness of barrier layer at the via bottom should be compromised because there exists contradiction between the two factors.
/
| 〈 |
|
〉 |