为了解决传统延时锁相环（DLL）结构在宽频率锁定范围中的无法锁定和谐波锁定问题,在传统DLL结构中加入启动控制电路,使DLL在上电阶段把环路滤波电容上的电压充电至电源电压,从而使压控延时线的初始延时在上电后达到最小,并且小于输入参考信号的1个周期.设计了带开关控制的鉴相器,将DLL的锁定过程分为粗调和微调两个阶段,压控延时线的延时在粗调阶段只能逐渐增大,在微调阶段微调,直到延时为输入参考信号的1个周期,从而克服了无法锁定以及谐波锁定的问题,而且减小了DLL的锁定时间.采用GSMC 0.13μm1P7MCMOS工艺设计、1.2 V的电源电压进行仿真,结果表明该DLL工作频率范围为300～500MHz,功耗小于3mW.

In order to avoid the failure lock and harmonic lock in conventional delay-locked loop（DLL） during wide-range operation,a start control circuit is added in the conventional DLL structure to charge the power supply by the loop filter capacitor in the power-on stage.So,the intitial delay of voltage-controlled delay line（VCDL） is minimized after the power-on and is controlled to be less than one period of the input reference clock.Then,a novel phase detector with switches is designed,which divides the locking process of DLL into a coarse tuning stage and a fine one.In the coarse tuing stage,the delay of VCDL monotonically increases,while in the fine stage,it is fine tuned till to one period of the input reference clock.Thus,the failure lock and harmonic lock during wide-range operation are successfully avoided and the the locking time of DLL is reduced.Finally,a DLL is designed and simulated under the power supply of 1.2V with GSMC 0.13μm 1P7M CMOS technology,with an operation frequency of 300～500MHz and a power consumption of less than 3mW being achieved.