针对 Tiny-yolo 网络模型规模大、占内存多、计算量大、不易在嵌入式端实现的问 题，提出了网络压缩、结合硬件加速的方法对其进行优化． 首先，分析网络连接关系，对网 络贡献较小的连接进行裁剪实现网络压缩，裁剪后的权值矩阵采用稀疏化存储方式减少 内存占用;其次，对权值进行量化，通过改变数据的位数，在保证精度误差范围内进一步减 小内存占用量和计算复杂度;最后，根据 Tiny-yolo 网络结构特点提出了深度并行 － 流水 的 FPGA 加速优化方案，最终实现了 Tiny-yolo 网络运算的硬件加速． 通过实验验证，网络 裁剪结合量化可以实现 36X 左右的压缩比率，通过硬件加速优化，相比在最大频率为 667 MHz 的 AＲM Cortex-A9 上运算实现了 7X 左右的运算加速．

Existing works based on Tiny-yolo often need large-scale network model，occupy more memories，rely on massive calculation and are not easy to deploy on embedded devices． To solve these problems，an efficient optimi- zation method on network compression and hardware acceleration was proposed． Firstly，connections which have less contribution to the network was pruned after analyzing the network connection relationship and sparse storage was adopted for the clipped weight matrix to reduce the memory consumption． Secondly，memory footprint and com- putational complexity within the guaranteed accuracy error was further reduced through quantifying the weight data and changing the number of digits． Finally，according to the characteristics of the Tiny-yolo network structure，a deep parallel-stream FPGA acceleration optimization scheme was proposed and the hardware acceleration of the Ti- ny-yolo network computation was achieved． Experiments demonstrate that the purposed method based on network pruning and quantization can achieve about 36X compression for network model and approximately 7X speedup compared with CPU by hardware acceleration．