采用0． 11μm 1P6M CMOS 工艺设计与研究了一款适用于蓝牙极性调制发射机 的两点调制锁相环． 为了校正锁相环中两个相位调制路径的环路增益，降低采用该锁相环 的发射机的频移键控误差，提出了一种新型的增益校正方法，并基于该方法设计了低相位 噪声、低锁定时间的两点调制锁相环电路． 芯片的测试结果表明，当压控振荡器震荡在 4． 8GHz时，该锁相环在偏离 4． 8 GHz 10 kHz、 1 MHz 和 3 MHz 时的相位噪声依次为 － 83、 －108和 －114dBc/Hz，采用该锁相环的极性调制发射机发射 0 dBm 信号时频移键控误差 为2． 97%，该锁相环的芯片面积为0． 32mm2，整体性能满足蓝牙射频芯片测试规范要求． 

Two-point modulation phaselocked loop ( PLL) for Bluetooth polar transmitter was studied and designed by using 0. 11μm 1P6M CMOS process． In order to correct the loop gain of two phase modulation paths in the PLL and reduce the frequency shift keying error of using the phaselocked loop，a new gain correction method was proposed． And a new phaselocked loop circuit of two-point modulation based on gain calibration was proposed to reduce phase noise of PLL and accelerate the locking time of phaselocked loop． Chip measured results show that when voltage controlled oscillator oscillates at 4. 8 GHz，the phase noises at 10 kHz，1 MHz，3 MHz offsets are －83dBc/Hz， －108dBc/Hz and －114dBc/Hz，respectively． When using the polar transmitter of phaselocked loop to transmit the 0dBm signal，the FSK error is 2. 97%，and the phaselocked loop occupies 0. 32 mm2． The overall performance meets the requirements of Bluetooth ＲF chip test specification．