设计了一个基于Pseudo-CMOS 逻辑门的低功耗异步复位D 触发器电路． 该D 触发器全部由n 型a-IGZO TFTs( 薄膜晶体管) 构成，采用动态负载替代Pseudo-CMOS 拓扑中的二极管连接负载，通过减少电路导通的概率来降低静态功耗． 电路的输出级为锁存器，通过反馈通路减少由动态负载造成的输出摆幅降低对延迟的影响． 将该D 触发器应用于环行移位寄存器的设计中，结果表明，该触发器电路可有效降低或非门逻辑电路中的静态功耗．  

Proposed in this paper is a low-power consumption D flip-flop circuit with asynchronous reset on the basis of Pseudo-CMOS logic gates,which consists of n-type a-IGZO TFTs ( Thin Film Transistors) ,replaces the diodeload in Pseudo-CMOS topology with dynamic load,and decreases the static power consumption by reducing the conduction probability of the circuit.The output stage of the circuit is a latch,and the effect of dynamic loadcaused output swing decrement on the delay is reduced through a feedback path.The proposed D flip-flop is then applied to the design of a ring shift register.The results show that the trigger circuit can reduce the static power consumption in NOR gate logic circuit effectively.