电容阵列数模转换器( DAC) 是逐次逼近型模数转换器( SAR ADC) 的主要能耗来源之一． 为降低电容阵列 DAC 的能耗，提出了一种高能效电容阵列 DAC 结构，该结构电容阵列中各电容单元通过开关依次连接． 在前两次比较周期中，由于采用了顶板采样和电压移位技术，电容阵列 DAC 没有产生能耗; 在之后的比较周期中，由于采用电荷共享和电压单调降低技术，电容阵列 DAC 产生了很少的能耗． 仿真结果表明，相比于传统的电容阵列 DAC
结构，文中提出的高能效电容阵列 DAC 结构可降低99. 22%的能耗，节省75%的面积．

Capacitor array digital-to-analogue converter (DAC) is one of the main energy consumption sources of
successive approximation register analogue-to-digital converter (SAR ADC)． In order to reduce the energy consumption of capacitor array DAC，this paper proposes a high energy-efficient capacitor array DAC structure． In the structure，each capacitor part is connected in turn through a switch． In the first two comparison cycles，owing to the top-plate sampling technique and the level shift technique，there is no switching energy consumption in the capacitor array DAC; in the rest of comparison cycles from the third to the nth，owing to the charge sharing technique and the voltage monotonic down technique，there exists a low switching energy consumption in the capacitor array DAC．
Simulation results show that，in comparison with the traditional capacitor array DAC structure，the proposed struc-
ture can decrease the energy consumption by 99． 22% and reduce the number of capacitors by 75%．