华南理工大学学报(自然科学版) ›› 2009, Vol. 37 ›› Issue (5): 38-42.

• 电子、通信与自动控制 • 上一篇    下一篇

JPEG2000中高性能低存储的小波变换结构

郭杰 吴成柯 李云松 马静   

  1. 西安电子科技大学 综合业务网理论及关键技术国家重点实验室, 陕西 西安 710071
  • 收稿日期:2008-05-15 修回日期:2008-11-12 出版日期:2009-05-25 发布日期:2009-05-25
  • 通信作者: 郭杰(1982-),男,博士生,主要从事图像压缩编码及其硬件实现研究. E-mail:jguo@mail.xidian.edu.cn
  • 作者简介:郭杰(1982-),男,博士生,主要从事图像压缩编码及其硬件实现研究.
  • 基金资助:

    国家自然科学基金重点项目(60532060);国家自然科学基金资助项目(60507012,60802076);西安电子科技大学博士创新基金资助项目(创05025)

High-Performance and Low-Memory Architecture of Wavelet Transform for JPEG2000

Guo Jie  Wu Cheng-ke  Li Yun-song  Ma Jing   

  1. State Key Laboratory of Integrated Service Networks, Xidian University, Xi'an 710071, Shaanxi, China
  • Received:2008-05-15 Revised:2008-11-12 Online:2009-05-25 Published:2009-05-25
  • Contact: 郭杰(1982-),男,博士生,主要从事图像压缩编码及其硬件实现研究. E-mail:jguo@mail.xidian.edu.cn
  • About author:郭杰(1982-),男,博士生,主要从事图像压缩编码及其硬件实现研究.
  • Supported by:

    国家自然科学基金重点项目(60532060);国家自然科学基金资助项目(60507012,60802076);西安电子科技大学博士创新基金资助项目(创05025)

摘要: 为改善整数离散小波变换的性能,提高图像压缩的质量,文中提出了一种JPEG2000中高性能低存储的离散小波变换结构.该结构扩展了原始图像数据的精度和有效保护了提升步骤中的系数尾数,采用码块条带的小波系数存储方案,对子带内的码块条带存储器进行重复利用和有效调度,从存储和功耗两方面减少了硬件资源.实验结果表明:该结构提高了图像压缩的质量;对分辨率为512×512的图像进行小波分解,码块大小选为32×32,采用文中结构的小波系数存储与存储整幅图像小波系数相比可减少80%.该结构已通过FPGA验证,且综合时钟频率可达到150MHz.

关键词: JPEG2000 离散小波变换, 提升算法, 码块, 超大规模集成电路

Abstract:

In order to improve the performance of integer discrete wavelet transform (DWT) and the compression quality of images, a DWT architecture with high performance and low memory is proposed for JPEG2000. This architecture extends the precision of raw image data and effectively preserves the fractional bits of transformed coeffi- cients in lifting steps. It adopts a memory scheme of wavelet coefficients based on code block strips to reuse and schedule the memories with code block strips in sub-bands, thus reducing the hardware resources in terms of sto- rage and power consumption. Experimental results show that the proposed scheme effectively improves the compres- sion quality of images, and that, by decomposing a 512 × 512 image using a code block in the size of 32 × 32, the memory of the proposed architecture is only 20% that of the scheme directly buffering all the coefficients in the transformed image. The proposed architecture has passed the FPGA verification and the synthesized clock frequency of it is up to 150 MHz

Key words: JPEG2000, discrete wavelet transform, lifting scheme, code block, VLSI circuits